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Reduced instruction set computing
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51	Bluespec Extensible RISC Implementation: BERI Hardware reference Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2015-04-14 11:22:52 Instruction set architectures Bluespec Inc. MIPS architecture Hardware description language Instruction set R4000 64-bit Reduced instruction set computing X86 debug register Computer architecture Computing Computer hardware
52	MIPS R5000 Microprocessor Technical Backgrounder Performance: SPECint95 Add to Reading List Source URL: www.sgidepot.co.uk Language: English - Date: 2008-04-15 15:08:30 MIPS architecture Central processing unit R4000 R4600 R8000 CPU cache R10000 R2000 Reduced instruction set computing Computer hardware Computer architecture R5000
53	SuperH™ (SH) 32-Bit RISC MCU/MPU Series SH7750 High-Performance RISC Engine Programming Manual Add to Reading List Source URL: mc.pp.se Language: English - Date: 1999-12-02 19:29:57 Central processing unit Instruction set architectures Virtual memory Computer memory Memory management unit SuperH CPU cache Reduced instruction set computing Addressing mode Computer architecture Computer hardware Computing
54	MIPS R5000 Microprocessor Technical Backgrounder Performance: SPECint95 Add to Reading List Source URL: vintagecomputers.info Language: English - Date: 1999-05-17 08:56:29 MIPS architecture Central processing unit R4000 R4600 R8000 CPU cache R10000 R2000 Reduced instruction set computing Computer hardware Computer architecture R5000
55	Ray Favre Jim Nagel And who outside it knew Ray Favre, one of Archive’s that for 25 years Ray was Add to Reading List Source URL: www.rayfavre.me.uk Language: English - Date: 2011-12-08 12:47:32 System software RISC OS WIMP Reduced instruction set computing BBC BASIC BBC Micro Software Computing Acorn Computers
56	TM SuperH (SH) 64-Bit RISC Series SH-5 CPU Core, Volume 4: Add to Reading List Source URL: lars.nocrew.org Language: English Computer hardware Microcontrollers SuperH Central processing unit Reduced instruction set computing Undefined behavior Processor register Comparison of CPU architectures Computer architecture Computing Instruction set architectures
57	Hot Chips 15 Janus – A Gigaflop RISC + VLIW SoC Tile Pier S. PAOLUCCI a,b,, Ben ALTIERI a, Federico AGLIETTI a, Stefano V. BASILE a, Piergiovanni BAZZANA a, Sergio BRUZZONE a, Alessandro CATASTA a, Antonio CERRUTO a, Add to Reading List Source URL: www.hotchips.org Language: English* - Date: 2013-08-12 00:06:24 Parallel computing Very long instruction word Reduced instruction set computing Instruction set Digital signal processing Digital signal processors Computer architecture Computing Computer hardware
58	Beyond Claims of Free Transistors and Abundant Instruction-Level Parallelism Michael D. Smith STANFORD UNIVERSITY Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 22:44:35 Computer engineering Parallel computing Superscalar Central processing unit Reduced instruction set computing Instruction-level parallelism Computing Computer architecture Classes of computers
59	Chips Symposium Santa Clara University Santa Clara, California Monday & Tuesday, August 20-21,1990 • Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 22:43:54 Microprocessors Institute of Electrical and Electronics Engineers Intel Reduced instruction set computing Multi-core processor Advanced Micro Devices Hot Chips Coprocessor MIPS Technologies Computer hardware Electronic engineering Computing
60	sunday August 18, 1996 Kresge Auditorium Sunday Tutorial Schedule 7:30 – 8:30 Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 22:47:32 Classes of computers Instruction set architectures Microprocessors Parallel computing Acorn Computers Reduced instruction set computing X86 Sun Microsystems Very long instruction word Computer architecture Computing Computer hardware